Citation :

Muthukumaran Vaithianathan, Mahesh Patil, Shunyee Frank Ng, Shiv Udkar, 2024. "Low-Power FPGA Design Techniques for Next-Generation Mobile Devices" ESP International Journal of Advancements in Computational Technology (ESP-IJACT)  Volume 2, Issue 2: 82-93.

Abstract :

FPGA are slowly becoming an indispensable part of the future mobile devices having flexible, high-performance modes and the capacity to speed up a lot of procedures. However, one of the main obstacles in integrating mobile devices into an application context is power management. This paper aims to identify and analyze several low-power design techniques for FPGAs in mobile devices in relation to power savings enhancement on various levels: architectural, circuit, and algorithmic. In this context, technologies that have been examined include dynamic voltage and frequency scaling technology (DVFS), power gating, clock gating, and advanced process technologies. The paper offers an overall literature on the latest technological development and approaches on Low power FPGA design; detailed methods for integrating these approaches and real time validation of these approaches are also added through simulations and case studies. The above conclusions show that, at present, choosing FPGAs as the main chip of the next generation of mobile devices can effectively save more power, thus providing an opportunity to develop more applications for FPGAs.

References :

[1] Rahul Awati, Dynamic voltage and frequency scaling (DVFS), Techtarget. https://www.techtarget.com/whatis/definition/dynamic-voltage-and-frequency-scaling-DVFS

[2] Clock Gating, Reddit, 2021. https://www.reddit.com/r/FPGA/comments/qgst96/clock_gating/?rdt=57640

[3] Johnson, M., & Brown, R. (2022). Advanced Power Gating Techniques for FPGA-Based Mobile Devices. IEEE Transactions on Circuits and Systems I: Regular Papers, 69(6), 2890-2903.

[4] Julian, Anitha , Mary, Gerardine Immaculate , Selvi, S. , Rele, Mayur & Vaithianathan, Muthukumaran (2024) Blockchain based solutions for privacy-preserving authentication and authorization in networks, Journal of Discrete Mathematical Sciences and Cryptography, 27:2-B, 797–808, DOI: 10.47974/JDMSC-1956

[5] Jason K. Lew, Low Power System Design Techniques Using FPGAs, Eetimes. https://www.eetimes.com/low-power-system-design-techniques-using-fpgas/

[6] Muthukumaran Vaithianathan, "Real-Time Object Detection and Recognition in FPGA-Based Autonomous Driving Systems," International Journal of Computer Trends and Technology, vol. 72, no. 4, pp. 145-152, 2024. Crossref, https://doi.org/10.14445/22312803/IJCTT-V72I4P119

[7] Chen, Y., & Tsai, M. (2020). A Survey of Low-Power Techniques for FPGA Design. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 28(2), 356-369.

[8] "Digital Signal Processing for Noise Suppression in Voice Signals", IJCSPUB - INTERNATIONAL JOURNAL OF CURRENT SCIENCE (www.IJCSPUB.org), ISSN:2250-1770, Vol.14, Issue 2, page no.72-80, April-2024, Available :https://rjpn.org/IJCSPUB/papers/IJCSP24B1010.pdf

[9] Muthukumaran Vaithianathan, Mahesh Patil, Shunyee Frank Ng, Shiv Udkar, 2023. "Comparative Study of FPGA and GPU for High-Performance Computing and AI" ESP International Journal of Advancements in Computational Technology (ESP-IJACT) Volume 1, Issue 1: 37-46.

Keywords :

Low-Power FPGA, Mobile Devices, Dynamic Voltage and Frequency Scaling (DVFS), Power Gating, Clock Gating, Architectural Optimization, Algorithm-Level Optimization.