Volume 1 Issue 2 | ESP IJCEET

Eternal Scientific Publication ESP

Volume 1 Issue 2 [July-September, 2023]

Id	Title & Author	Paper
1	Design of Delay Efficient Multiplier Using Parallel Prefix Adders \| C V P Supradeepthi, B Veena, M Hima Bindu As technology advances, the demand for speedy and efficient real-time digital signal processing applications has grown. Every application requires multiplication as one of the main arithmetic operations. To boost their speed, a vast number of multiplier designs have been devised. A new technique for designing High-Speed multipliers is proposed in this work. With four 8X8 approximate multipliers, three parallel prefix adders [PPA], and one OR gate, this proposed 16X16 approximate multiplier construction is offered.
2	Environmental Factors Independent System for Plants’ Growth \| Adewale Abayomi Alabi, Bolarinwa Samson Adeleke, Taiwo Ganiyu Fawole Due to incessant increase in global population and unpredictable nature of environmental conditions, food availability to meet population demand has become a threat. This menace to human populace will continue until serious efforts are shifted to controlled environmental agriculture (CEA) and ensure there is urgent change of food production systems.
3	Design and Analysis of RADIX-8 Based 32-bit Pipelined Multiplier \| Mummareddy Ramya Krishna, B. Ramana Kumar In microprocessors, microcontrollers, and signal processing applications, arithmetic operations are essential. Digital Signal Processing (DSP) modules such as Infinite Impulse Response (IIR) filters, Finite Impulse Response (FIR) filters, Discrete Fourier Transform (DFT), Fast Fourier Transform (FFT), Discrete Cosine Transform (DCT), and others frequently employ the multiplication operation.
4	A Low Power 6T SRAM using Sleep Power Reduction Technique \| Lakshmi Durga Nujiveeti, R Vinay Kumar One type of memory component is static random access memory (SRAM). SRAM is in high demand in SOCs due to its unique data-retention capabilities. For the sake of anticipating future needs, this memory part became the subject of study. The importance of power leakage in chip design has grown as SRAM densities have increased. Recent years have seen significant progress in SRAM's ability to reduce power consumption.
5	On-Chip Permutations Network Design with a Three-Dimensional Mesh Network \| Reena Kumari, Mohammad Ismail Khattab The network on chip (NoC) is being investigated as an on-chip communication fabric for future multiprocessor system on chips (MPSOCs) because of its adaptability, scalability, and high bandwidth. My abstract describes the methodology behind the construction of a network-on-chip that can sustain a specified throughput. Using three layers of 4-port switches in a closed network configuration.

Id	Title & Author	Paper
1	Design of Delay Efficient Multiplier Using Parallel Prefix Adders \| C V P Supradeepthi, B Veena, M Hima Bindu As technology advances, the demand for speedy and efficient real-time digital signal processing applications has grown. Every application requires multiplication as one of the main arithmetic operations. To boost their speed, a vast number of multiplier designs have been devised. A new technique for designing High-Speed multipliers is proposed in this work. With four 8X8 approximate multipliers, three parallel prefix adders [PPA], and one OR gate, this proposed 16X16 approximate multiplier construction is offered.
2	Environmental Factors Independent System for Plants’ Growth \| Adewale Abayomi Alabi, Bolarinwa Samson Adeleke, Taiwo Ganiyu Fawole Due to incessant increase in global population and unpredictable nature of environmental conditions, food availability to meet population demand has become a threat. This menace to human populace will continue until serious efforts are shifted to controlled environmental agriculture (CEA) and ensure there is urgent change of food production systems.
3	Design and Analysis of RADIX-8 Based 32-bit Pipelined Multiplier \| Mummareddy Ramya Krishna, B. Ramana Kumar In microprocessors, microcontrollers, and signal processing applications, arithmetic operations are essential. Digital Signal Processing (DSP) modules such as Infinite Impulse Response (IIR) filters, Finite Impulse Response (FIR) filters, Discrete Fourier Transform (DFT), Fast Fourier Transform (FFT), Discrete Cosine Transform (DCT), and others frequently employ the multiplication operation.
4	A Low Power 6T SRAM using Sleep Power Reduction Technique \| Lakshmi Durga Nujiveeti, R Vinay Kumar One type of memory component is static random access memory (SRAM). SRAM is in high demand in SOCs due to its unique data-retention capabilities. For the sake of anticipating future needs, this memory part became the subject of study. The importance of power leakage in chip design has grown as SRAM densities have increased. Recent years have seen significant progress in SRAM's ability to reduce power consumption.
5	On-Chip Permutations Network Design with a Three-Dimensional Mesh Network \| Reena Kumari, Mohammad Ismail Khattab The network on chip (NoC) is being investigated as an on-chip communication fabric for future multiprocessor system on chips (MPSOCs) because of its adaptability, scalability, and high bandwidth. My abstract describes the methodology behind the construction of a network-on-chip that can sustain a specified throughput. Using three layers of 4-port switches in a closed network configuration.

ESP International Journal of Communication Engineering & Electronics Technology (ESP-IJCEET)

Volume 1 Issue 2 [July-September, 2023]